1. Field of the Invention
The present invention relates to electrically programmable read only memories (EPROMs) and, in particular, to a method for reducing the spacing between the horizontally-adjacent floating gates of the storage cells in a flash EPROM array.
2. Discussion of the Related Art
A flash electrically programmable mad-only-memory (EPROM) is a non-volatile memory that, like conventional EPROMs, retains data which has been stored in the memory when power is removed and which, unlike conventional EPROMs, can be selectively erased.
FIG. 1 shows a plan view of a portion of a conventional "T-shaped" flash EPROM array 10. As shown in FIG. 1, array 10 includes a series of memory cells 12 and a series of field oxide regions FOX which isolate the horizontally-adjacent memory cells of the array. In addition, each memory cell 12 in a row of memory cells shams a common source bit line CSBL with the remaining memory cells 12 in the row, and with the memory cells 12 in a vertically-adjacent row of memory cells. Each memory cell 12 also shares a common drain contact 14 with one vertically-adjacent memory cell 12.
FIG. 2 shows a cross-sectional diagram taken along lines 1A--1A of FIG. 1 that illustrates the structure of an individual memory cell 12. As shown in FIG. 2, each memory cell 12 includes a floating gate 16 and a composite layer of oxide/nitride/oxide (ONO) 18 which is formed over floating gate 16. In addition, each floating gate 16 is isolated from a horizontally-adjacent floating gate 16 by a layer of edge oxide 20.
The memory cells 12 in a row of memory cells 12 are then connected together by a word line 22 which is formed over the layers of ONO 18 and the layers of edge oxide 20. As is well known, the portion of the word line 22 which is formed over each of the floating gates 16 functions as the control gate of the memory cell.
One of the major goals in the design of a T-shaped flash EPROM is to increase the density of the memory array. Historically, the density of the array has been increased by photolithographically reducing the area consumed by each cell of the array as measured by the pitch of the cells in the X direction and the pitch of the cells in the Y direction.
The pitch of a cell in the X direction can be measured as the distance from one edge of a floating gate to the same edge of a horizontally-adjacent floating gate. Thus, as shown in FIGS. 1 and 2, the X cell pitch is partially defined by the distance D.sub.1 which represents the spacing between the horizontally-adjacent floating gates 16 of the array.
As further shown in FIGS. 1 and 2, the remainder of the X cell pitch is defined by the distances D.sub.2' and D.sub.2", which represent the horizontal component of the portion of the floating gates which are formed over the adjacent field oxide regions FOX, known as the wings of the floating gates, and the distance D.sub.3, which represents the channel width.
In a conventional flash EPROM fabrication process, the floating gates 16, which are formed from a layer of polysilicon (poly1), are initially defined by depositing a layer of poly1, followed by an overlying layer of dielectric material, e.g., ONO. The spacing between the horizontally-adjacent floating gates is then photolithographically defined by masking and etching the layer of dielectric material and the underlying layer of polysilicon.
Thus, when an n micron photolithographic process is utilized, where n represents the minimum feature size that can be obtained by that process, the minimum spacing between horizontally-adjacent floating gates is limited by the minimum feature size that can be photolithographically obtained with that process. For example, if a 0.6 micron photolithographic process is utilized, the minimum floating gate spacing is limited to 0.6 microns.
Further, when an n micron photolithographic process is utilized, the minimum size of both the wings and the channel width are defined by the requirements of the cell, i.e., the read current level, the gate coupling level. Thus, the X cell pitch is limited by the minimum floating gate spacing that can be photolithographically obtained, and the practical size requirements of the wings and channel of the cell.
Since the photolithographic process limits the minimum size of the floating gate spacing, rather than the requirements of the cells, there is a need for a process which can reduce the floating gate spacing beyond that which is photolithographically obtainable by a given process.